The inventive concept relates to semiconductor memory devices, and more particularly to a method of determining a read voltage for non-volatile semiconductor memory devices. The inventive concept also relates to memory cards and memory systems incorporating such memory devices.
Semiconductor memory devices (hereafter, “memory devices”) include volatile memory devices and non-volatile memory devices. Volatile memory devices are generally characterized by fast data access write speeds, but lose stored data in the absence of applied power. In contrast, non-volatile memory devices generally provide slower data access speeds but retain stored data in the absence of applied power.
Conventional nonvolatile memory devices include phase-change random access memory (PRAM), mask read-only memory (MROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM). With respect to MROM, PROM, and EPROM among nonvolatile memory devices, it is relatively difficult for users to enter (or update) data since erase and write operations cannot be freely performed. On the other hand, data may be electrically erased and written in EEPROM. Because of this ease of use, EEPROM has been increasingly used in various systems (including auxiliary data storage devices) as a data storage media for programming as well as payload data.
Within the broader class of EEPROM devices, flash EEPROM (hereinafter, “flash memory”) is characterized by high integration density of memory elements and is thus very advantageous when used as a large-capacity auxiliary memory device. Accordingly, many types of flash memory are widely used in small electronic devices such as the digital camera, digital camcorder, digital music player, etc. These devices particularly benefit from the high data storage capacity, easy data access capabilities, and compact size of flash memory.
In its operation, flash memory determines whether electrons have been injected onto a floating gate via a conventionally understood phenomenon known as Fowler-Nordheim (F-N) tunneling. That is, the quantity of injected electrons on the floating gate may be interrupted as respective data states for a memory cell in flash memory (e.g., first and second logic levels for a binary memory cell). For example, during a program operation, a voltage of 15V is applied to the gate of the selected memory cell to enable F-N tunneling. As F-N tunneling proceeds and a greater quantity of electrons are injected onto the floating gate, the threshold voltage (Vth) of the memory increases. During an erase operation, a voltage of 20V is applied to the body (or semiconductor bulk) of the selected memory cell to again enable F-N tunneling. However, the flow of electrons from the floating gate during the erase operation is the reverse of the flow of electrons to the floating gate during the program operation. Accordingly, during the erase operation the threshold voltage Vth of the memory cell decreases.
Due to certain well known operating characteristics related to flash memory, the repeated execution of program and erase operations (or program/erase cycles) stresses and ultimately deteriorates the thin gate oxide film through which electrons pass during F-N tunneling. Once the gate oxide film deteriorates to a certain degree it is no longer capable of preventing the discharge, over time, of electrons injected onto the floating gate. This unintended discharge of electrical charge decreases the threshold voltage of the memory cell. Figure (FIG. 1 illustrates this life-cycle characteristic of flash memory.
FIG. 1 shows the migration of threshold voltage characteristics for a flash memory cell over its useful life (i.e., over a number of program/erase cycles). In FIG. 1, the upper graph (a) shows a memory cell threshold voltage distribution (hereafter “cell distribution”) just after a successful program operation. The comparative lower graph (b) shows the cell distribution for the same flash memory cell following a period of time after programming. This drift in threshold voltage caused by a loss of stored charge through a deteriorated gate oxide film is symptomatic of a heavily worn flash memory cell (i.e., a memory cell degraded in its data storage capabilities by numerous program/erase cycles).
Referring to the graphs (a) and (b) of FIG. 1, it can be seen that the overall field of threshold voltage states (e.g., erase and P1-P7) for the flash memory cell is shifted to the left by generally reduced threshold voltage levels. Further, threshold voltage distribution broadening is apparent as respective threshold voltages become less distinct over time. Ultimately, the combined effects of shifted (reduced) threshold voltages and less distinct threshold voltages make data discrimination during a read operation to a heavily worn flash memory cell quite difficult, if not impossible.
The foregoing effects notwithstanding, a flash memory cell's threshold voltage distribution may also be shifted in the other direction (i.e., increased) by so-called coupling effects between proximate memory cells during program operations. Here again, any undesired shift (up or down) and/or broadening/narrowing of a threshold voltage distribution (collectively or individually “threshold voltage migration”), regardless of underlying cause, may result in data errors during subsequent read operations.